1. Field of the Invention
The present invention relates to an analog signal sampling circuit, constructed with field-effect transistors, for use in a successive-approximation A/D converter or the like, and more particularly to a sampling circuit containing an inverting amplifier and a capacitor wherein the input to the capacitor is switched in accordance with a clock signal between a signal voltage to be measured and a reference voltage, while the input and output of the inverting amplifier are short-circuited in accordance with the clock signal, thus obtaining an output proportional to the difference between the signal voltage and reference voltage held in the capacitor.
2. Description of the Related Art
In recent systems, a digital signal converted from an analog signal is processed at high speed using a digital signal processor (DSP). The digital signal thus processed is converted back into an analog signal for output, or is stored in memory. With recent advances in MOS (metal-oxide semiconductor) and MES (metal semiconductor) technologies, the functional capabilities and operating speeds of DSPs have been increasing rapidly, and at the same time, it has become possible to accommodate an A/D converter and D/A converter on the same chip with a DSP, thus making possible the construction of a desired circuit with fewer chips. In such an A/D converter, an analog signal sampling circuit is often used.
A typical analog signal sampling circuit comprises an inverting amplifier, a capacitor, a first switch for switching the input to the capacitor between a sampled signal voltage and a reference signal in accordance with a clock signal, and a second switch for connecting and disconnecting the input terminal of the inverting amplifier to and from the output terminal thereof in accordance with the clock signal. With the first and second switches alternately conducting in accordance with the clock signal, the inverting amplifier outputs a voltage that is proportional to the difference between the signal voltage and the reference voltage.
In such an analog signal sampling circuit, a parasitic capacitance is present between the input terminal of the inverting amplifier and the gate of the second switch. Since the voltage on one plate of this parasitic capacitance changes with the clock signal, the amount of charge stored in the parasitic capacitance changes according to the state of the clock signal, which affects the voltage being applied to the input terminal of the inverting amplifier, resulting in an error.
In low-resolution A/D conversion systems, this error does not present any serious problems, but in high-resolution A/D conversion systems, this error is not negligible; hence, there arises the need to reduce this error.